@jeffcliff@admitsWrongIfProven@sjw I don't have screenshots or shit yet to show but who wants to watch me make an RV32I core in a visual manner
Hoping to get to RV64G + Supervisor eventually
@jeffcliff@p@sjw@ceo_of_monoeye_dating@ai In theory, a complete RV32I core, and where I left off a few years ago (following along a YouTube video)
In reality, there were a couple bugs that I got stuck on, but hopefully I've bridged that gap in knowledge
But, that's for tomorrow :akko_tired: Screenshot_2023-11-30_00-59-52.png
> can't use ROM chips without extra work because it'll fuck up using compressed instructions because no non-aligned memory access
> can't use RAM chips because I can't edit the stored data
@ai@ceo_of_monoeye_dating@jeffcliff@p@sjw nvm I think something may be bugged with auipc
Doesn't seem to be actually adding in the PC?
Hmmm
I'm gonna build up some proper tests to make sure I'm not misunderstanding something
@jeffcliff@ceo_of_monoeye_dating@sjw@ai@p I believe that's write enable, it's being held high rn but I would like to keep it around in case I want to try pipelining
@ai@ceo_of_monoeye_dating@jeffcliff@p@sjw That being said, I'm gonna have to do a lot of digging into microarchitecture and that sort of meta-logic very soon in order to make those instructions work, and to get a unified memory architecture
@ai@ceo_of_monoeye_dating@jeffcliff@p@sjw I feel now would be a good time to try and figure out how to unify the memory space, because before I can implement CSRs, I'm probably going to want to add atomics
I want to keep it stupid simple at first though
... also I just realized I overwrote the base core...
@ai@ceo_of_monoeye_dating@jeffcliff@p@sjw uhhhhh ok yeah this is an interesting hurdle
Multi cycle architecture never quite clicked with me but I think the amount of stuff in front of my face is distracting me
@ceo_of_monoeye_dating@ai@jeffcliff@p@sjw well tbh pipelines are more foreign to me, I've never really strayed far from single cycle simulation, but that doesn't work if I want to fetch instructions and data from the same place
@ai@ceo_of_monoeye_dating@jeffcliff@p@sjw wait
Fuck
If I want to move to rv64 I'm gonna need 64bit data
Which the unaligned chip doesn't do...
So I'm going to have to make a new chip anyway
@ai@ceo_of_monoeye_dating@jeffcliff@p@sjw Ughhhhh this is foreign waters to me
I'm trying to go through the Spike simulator codebase to glean what I can about how CSRs and privileges ISA is supposed to work and it's all blurring together
@ai@ceo_of_monoeye_dating@jeffcliff@p@sjw Ok so in theory I can use this to get a better idea of how to pipeline this shit, and eventually add things like branch prediction and cache
It's going to be.... a lot of work but at least now I have a diagram to read https://arxiv.org/pdf/2002.03568v1.pdf
I also found a sim file for a pipelined MIPS CPU with full hazard detection so 🤞
@ai@ceo_of_monoeye_dating@jeffcliff@p@sjw I wonder if I have enough information in front of me here to piece together something from verilog files
Might help me make sense of whatever the fuck I'm staring at
@ai@ceo_of_monoeye_dating@sjw@p@jeffcliff I've left off in the middle of the compressed instruction decoder, so that I can use it to control the instruction length plexer and it doesn't change anything about the later stages (yet, will need exceptions and traps eventually)
Control lines are so much more clean now, and getting more clean as I go
To be fair I'm stealing it from RIPES but I can work from there
@ai@ceo_of_monoeye_dating@jeffcliff@p@sjw almost done with quadrant 2, thinking about going ahead and throwing in the exception generation logic while I'm at it
Had fun getting flood trapped away from home yesterday but it ended up resulting in me getting 12 hours of sleep so yeah
@jeffcliff@ceo_of_monoeye_dating@sjw@ai@p Oh sorry, just the compressed extension
I've still got a lot of work cleaning up the rest of the pipeline
Biting the bullet and using subcircuits, at the cost of having all the logic front and center to look at
Cleaned up the decode stage image.png
@jeffcliff@ai@ceo_of_monoeye_dating@p@sjw And if we want to talk about VHDL...
Well there's already better implementations that actually have interrupt logic and formal verification
Eventually, though
Gotta catch up on finances (again) and then I plan on getting a proper dev board
@jeffcliff@ceo_of_monoeye_dating@sjw@ai@p Well there really isn't a way for this sim to access external programs or devices, but there is simulated MMIO like VGA, a terminal, a keyboard, 7-segment displays and such
I'm stuck designing the busses though
@jeffcliff@ai@ceo_of_monoeye_dating@p@sjw Also it's all running in Java so I'm gonna have to fuck around with heap space, otherwise I'm stuck with 24-bit memory blocks
@ai@ceo_of_monoeye_dating@jeffcliff@p@sjw need the hazard and forwarding units and should be fully functional once I'm there, minus syscalls and traps and shit
There's a few things I need to tinker with to simplify but I can worry about that later image.png
@ai@ceo_of_monoeye_dating@jeffcliff@p@sjw My control unit is a huge mess of combinational logic
It's so easy to tell a lot of lines were forced to be translated into and out of enum values
And it's all going to have to be redone as soon as I try to add more features
But it works, I think
Going through trying to hook them up and I'm seeing control lines that aren't explicitly diagrammed by RIPES and look suspiciously like things I need more ISA for...
REEEEEE
Getting closer image.png
@ai@ceo_of_monoeye_dating@jeffcliff@p@sjw most notable, it seems like the ecall checker used by RIPES is specifically designed to hook into the external program, which I obv can't do if I want to follow the standard or like
Treat it like physical hardware
I am far beyond the point where I have any actual understanding of what I'm doing
If anyone knows more what I'm looking at or knows someone who does any input or tips would be appreciated, it's a lot more helpful than just staring at the same doc pages all day (am afk atm, at work)
@ai@ceo_of_monoeye_dating@jeffcliff@p@sjw Let's see, external IO...
That means I'm probably going to want an external reset pin, especially if I want to add multiple cores and threads, an external interrupt pin, whatever pins UART or whatever analogue I decide to use needs...
I'm probably going to have to rewrite it halfway from scratch just to manage new cabling
@ai@ceo_of_monoeye_dating@jeffcliff@p@sjw Actually
Yeah
I wanna get to the all out point eventually
8 harts, 4 cores
L1 through L3 cache, 8 ways
PCI of some sort
Vector extensions at some point
Full privileged ISA support
The whole shebang
@ai@ceo_of_monoeye_dating@jeffcliff@p@sjw fuckkk me nvm on the fancy stuff for now
I forgot things like PCI use special signaling and things to work
So
As external interface to a theoretical processor, knowing what I know about, say, the 8086, I know I'd need...
A Non-Maskable Interrupt pin
A maskable Interrupt
External reset
Data bus
Address bus
Write/read enable for memory access
Looks like I might need Cache Flush and Enable, as well as maybe a way to implement Burst Access?
A lot of the pins are x86 specific (duh) so I'm uncertain how many of these need to be kept between ISAs
@ai@ceo_of_monoeye_dating@jeffcliff@p@sjw I'd say I'd like to reach a point where this thing could be fabbed and be a drop-in replacement for Intel or AMD but I realize that motherboard sockets and designs themselves are locked into x86
@ai@ceo_of_monoeye_dating@jeffcliff@p@sjw ughhhh trying not to burn out on this
Ok
So
I just want, to begin with
One RV64GC core
I'm okay with emulating atomics if need be
I would like CLINT if possible
Some sort of cache and burst mode addressing will probably be needed for that
But I want it to be ready to add another hart at some point
@ai@ceo_of_monoeye_dating@jeffcliff@p@sjw There's plenty of IP cores available but they all rely on FPGAs and AXI and shit and I'm not ready for that :blobcatfearful:
@ai@ceo_of_monoeye_dating@jeffcliff@p@sjw I'm getting more comfortable with the thought of AXI now that I'm seeing how 1) logisim has combinatorial and FSM generation
And 2) verilog lays them out pretty plainly
@ai@ceo_of_monoeye_dating@jeffcliff@p@sjw This is the topmost file, each cache and the CPU will get dropped here
And by that I mean temporarily, and then I'll move the caches down a layer into the CPU once I'm sure things are working image.png
@ai@ceo_of_monoeye_dating@jeffcliff@p@sjw THAT BEING SAID
I am now tired
I am going to have to repeat a lot of this to do the icache (Not all of it thank god, but it has a slightly different FSM and AXI interface it seems)
@TURBORETARD9000@ai@jeffcliff@p@sjw Neither do I. I barely scraped through my Comp Arch class, and that was more than 10 years ago. I can maybe give broad suggestions sometimes but that's it.
@ceo_of_monoeye_dating@ai@jeffcliff@p@sjw I have the Risc-V ISA specs on hand, need to grab AMBA4 for the AXI spec
After that fuck if I know what docs I need to grab to understand what I'm doing
@ai@ceo_of_monoeye_dating@jeffcliff@p@sjw Also it seems I could've done just the CPU and TCM (fuck yeah we got that too, 64KB of it) and that would've been enough to test the CPU itself
I'm not complaining tho
@ai@ceo_of_monoeye_dating@jeffcliff@p@sjw ughhh ok so I know this is a mux but it always bugs me when 1) they define what looks like the default statement up at the top under begin but then have a different default below, and 2) when there's more mux input slots than case statements
It feels weird image.png
@ai@ceo_of_monoeye_dating@jeffcliff@p@sjw Ok I finished both icache and dcache
I need to figure out how to test them before going further, because it's just gonna piss me off if I get everything finished and pieces don't work dcache icache
@jeffcliff@ceo_of_monoeye_dating@sjw@ai@p This is an examplke of what ius in actaul IRL processors
Well, sorta, most processors nowadays are like
8-way, LRU replacement policy caches
Onde I test these I can easily upgrade
@jeffcliff@ai@ceo_of_monoeye_dating@p@sjw That being said
I don't quite know how to test these yet
I have a surface understanding each of AXI, cache, and test vectors but I'll still need to experiment how to put those pieces together
Also will need to eventually figure out how to upgrade these to 64-bit words for RV64
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